Using a diffusion wavelet neural network for short-term time series learning in the wafer level chip scale package process

Der Chiang Li, Chun Wu Yeh, Chieh Chih Chen, Hung Ta Shih

研究成果: Article

1 引文 斯高帕斯(Scopus)

摘要

Wafer level chip scale packages (WLCSP) have the advantages of high efficiency, high power and high density, and can ensure the consistent printed circuit board assembly necessary to achieve high yield and reliability. WLCSP are attracting more attention as electronic devices continue to become smaller and more portable. Although this package technology can enhance electronic signal input/output density, there is often the problem of a low yield in the early stage of its introduction. Several manufacturing factors influence the packaging process, with the height of the solder balls on multilayer metallic film being the decisive one. Due to the very few samples produced in pilot runs in the early stages of new product development, statistical process control charts can only provide limited information. This study is based on the idea of timeline division, and proposes a diffusion wavelet neural network which uses the correlated virtual sample generating method to improve its predictive performance for short-term time series. The diffusion wavelet neural network can improve the predictive accuracy more effectively than either a back-propagation neural network or a grey-based forecasting method.

原文English
頁(從 - 到)1261-1272
頁數12
期刊Journal of Intelligent Manufacturing
27
發行號6
DOIs
出版狀態Published - 2016 十二月 1

    指紋

All Science Journal Classification (ASJC) codes

  • Software
  • Industrial and Manufacturing Engineering
  • Artificial Intelligence

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