Simulation methodologies have been widely utilized to aid hardware/software co-design and shorten the development cycles of systems-on-chips (SoCs). For a complex multicore system, traditional hardware description languages (HDLs), such as Verilog and VHDL, consume too much time in a simulation and are far too slow to perform parallel programs and modern operating systems. Instead, SystemC provides a higherlevel environment to reduce the simulation time and is often a better choice for hardware/software co-design. For existing HDL-based chip designs, it is possible to automatically convert them to SystemC or even higher-level functional descriptions to improve the simulation speed and enable hardware/software co-design. However, existing tools failed to accomplish that for a complex multicore SoC, such as the OpenSPARC T1. Therefore, we investigated the problems encountered by two most popular converting tools, Verilator and V2SC, and developed our own tool, called V2X, to overcome the problems. In our case study, V2X successfully translated the 8-core OpenSPARC T1 SoC (approximately 300,000 lines of Verilog code) into SystemC and significantly reduced the simulation time by 40 times for the user. In addition, this article discusses the two-stage translation scheme which makes V2X more powerful than existing tools and the quick replay method for automatic generation of chip verification suites for the new SystemC-based simulation.
|頁（從 - 到）||48-62|
|期刊||Journal of the Chinese Institute of Engineers, Transactions of the Chinese Institute of Engineers,Series A|
|出版狀態||Published - 2013 一月|
All Science Journal Classification (ASJC) codes
- 工程 (全部)