Variability study of silicon nanowire FETs

Yi Bo Liao, Meng-Hsueh Chiang, Keunwoo Kim, Wei-Chou Hsu

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

In this work, impact of device variability for silicon nanowire FETs is assessed and SRAM design implication is presented based on 3-D numerical simulation. Both the conventional and junctionless nanowire FETs are shown to be sensitive to structural variation whereas the former is more tolerable. Both the circular wire and non-circular wire cases for feasible SRAM design with a focus on read noise margin are included in our study.

原文English
主出版物標題Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011
頁面46-49
頁數4
出版狀態Published - 2011 十一月 23
事件Nanotechnology 2011: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011 - Boston, MA, United States
持續時間: 2011 六月 132011 六月 16

出版系列

名字Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011
2

Other

OtherNanotechnology 2011: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011
國家/地區United States
城市Boston, MA
期間11-06-1311-06-16

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程

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