This paper benchmarks the performance of gate-all-around (GAA) MOSFETs against that of optimized silicon-on-insulator FinFETs at 10-nm gate length. Variability in transistor performance due to systematic and random variations is estimated with the aid of TCAD 3-D device simulations, for both device structures. The yield of six-transistor SRAM cells implemented with these advanced MOSFET structures is then investigated via a calibrated physically based compact model. The GAA MOSFET technology is projected to provide for 0.1 V lower minimum cell operating voltage with reduced cell area.
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