Very high speed continuous sampling using matched delays

S. M. Clements, W. Liu, J. Kang, R. K. Cavin

研究成果: Article同行評審

1 引文 斯高帕斯(Scopus)

摘要

The authors describe a scheme for very high speed continuous sampling of digital data. It is based on a high speed non-continuous sampling device that uses matched data and clock delay lines. The frquency of the sample clock necessary for continuous sampling is derived, and the components needed to deskew and synchronise the latch outputs for storage in an output register are detailed.

原文English
頁(從 - 到)463-465
頁數3
期刊Electronics Letters
30
發行號6
DOIs
出版狀態Published - 1994 3月 3

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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