Very low Vt [Ir-Hf]/HfLaO CMOS using novel self-aligned low temperature shallow junctions

C. F. Cheng; C. H. Wu; N. C. Su; S. J. Wang; S. P. McAlister; Albert Chin

doi:10.1109/IEDM.2007.4418939

Very low V_t [Ir-Hf]/HfLaO CMOS using novel self-aligned low temperature shallow junctions

C. F. Cheng, C. H. Wu, N. C. Su, S. J. Wang, S. P. McAlister, Albert Chin

微電子工程研究所

研究成果: Conference article › 同行評審

33 引文斯高帕斯（Scopus）

摘要

We report very low V_t [Ir-Hf]/HfLaO CMOS using novel self-aligned low-temperature ultra shallow junctions with gate-first process compatible with current VLSI. At 1.2 nm EOT, good φ_m-eff of 5.3 and 4.1 eV, low V_t of +0.05 and 0.03 V, high mobility of 90 and 243 cm²/Vs, and small 85°C BTI <32 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS.

原文	English
文章編號	4418939
頁（從 - 到）	333-336
頁數	4
期刊	Technical Digest - International Electron Devices Meeting, IEDM
DOIs	https://doi.org/10.1109/IEDM.2007.4418939
出版狀態	Published - 2007
事件	2007 IEEE International Electron Devices Meeting, IEDM - Washington, DC, United States 持續時間: 2007 12月 10 → 2007 12月 12

All Science Journal Classification (ASJC) codes

電子、光磁材料
凝聚態物理學
電氣與電子工程
材料化學

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10.1109/IEDM.2007.4418939

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title = "Very low Vt [Ir-Hf]/HfLaO CMOS using novel self-aligned low temperature shallow junctions",

abstract = "We report very low Vt [Ir-Hf]/HfLaO CMOS using novel self-aligned low-temperature ultra shallow junctions with gate-first process compatible with current VLSI. At 1.2 nm EOT, good φm-eff of 5.3 and 4.1 eV, low Vt of +0.05 and 0.03 V, high mobility of 90 and 243 cm2/Vs, and small 85°C BTI <32 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS.",

author = "Cheng, {C. F.} and Wu, {C. H.} and Su, {N. C.} and Wang, {S. J.} and McAlister, {S. P.} and Albert Chin",

year = "2007",

doi = "10.1109/IEDM.2007.4418939",

language = "English",

pages = "333--336",

journal = "Technical Digest - International Electron Devices Meeting, IEDM",

issn = "0163-1918",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2007 IEEE International Electron Devices Meeting, IEDM ; Conference date: 10-12-2007 Through 12-12-2007",

}

TY - JOUR

T1 - Very low Vt [Ir-Hf]/HfLaO CMOS using novel self-aligned low temperature shallow junctions

AU - Cheng, C. F.

AU - Wu, C. H.

AU - Su, N. C.

AU - Wang, S. J.

AU - McAlister, S. P.

AU - Chin, Albert

PY - 2007

Y1 - 2007

N2 - We report very low Vt [Ir-Hf]/HfLaO CMOS using novel self-aligned low-temperature ultra shallow junctions with gate-first process compatible with current VLSI. At 1.2 nm EOT, good φm-eff of 5.3 and 4.1 eV, low Vt of +0.05 and 0.03 V, high mobility of 90 and 243 cm2/Vs, and small 85°C BTI <32 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS.

AB - We report very low Vt [Ir-Hf]/HfLaO CMOS using novel self-aligned low-temperature ultra shallow junctions with gate-first process compatible with current VLSI. At 1.2 nm EOT, good φm-eff of 5.3 and 4.1 eV, low Vt of +0.05 and 0.03 V, high mobility of 90 and 243 cm2/Vs, and small 85°C BTI <32 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS.

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U2 - 10.1109/IEDM.2007.4418939

DO - 10.1109/IEDM.2007.4418939

M3 - Conference article

AN - SCOPUS:50249162020

SN - 0163-1918

SP - 333

EP - 336

JO - Technical Digest - International Electron Devices Meeting, IEDM

JF - Technical Digest - International Electron Devices Meeting, IEDM

M1 - 4418939

T2 - 2007 IEEE International Electron Devices Meeting, IEDM

Y2 - 10 December 2007 through 12 December 2007

ER -

Very low Vt [Ir-Hf]/HfLaO CMOS using novel self-aligned low temperature shallow junctions

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Very low V_t [Ir-Hf]/HfLaO CMOS using novel self-aligned low temperature shallow junctions