VLSI Architecture for 2-D 3-Level Lifting-Based Discrete Wavelet Transform

Pel Yin Chen

VLSI Architecture for 2-D 3-Level Lifting-Based Discrete Wavelet Transform

資訊工程學系

研究成果: Article › 同行評審

摘要

Discrete wavelet transform has been successfully used in many image processing applications. In this paper, we present an efficient VLSI architecture for 2-D 3-level lifting-based discrete wavelet transform using the (5, 3) filter. All three-level coefficients are computed interlacingly and periodically to achieve higher hardware utilization and better throughput. In comparison with other VLSI architectures, our architecture requires less size of storage and faster computation speed.

原文	English
頁（從 - 到）	275-279
頁數	5
期刊	IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
卷	E87-A
發行號	1
出版狀態	Published - 2004 1月

All Science Journal Classification (ASJC) codes

訊號處理
電腦繪圖與電腦輔助設計
電氣與電子工程
應用數學

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引用此

@article{7bf2c39c70b24794a9693c983e53ea24,

title = "VLSI Architecture for 2-D 3-Level Lifting-Based Discrete Wavelet Transform",

abstract = "Discrete wavelet transform has been successfully used in many image processing applications. In this paper, we present an efficient VLSI architecture for 2-D 3-level lifting-based discrete wavelet transform using the (5, 3) filter. All three-level coefficients are computed interlacingly and periodically to achieve higher hardware utilization and better throughput. In comparison with other VLSI architectures, our architecture requires less size of storage and faster computation speed.",

author = "Chen, {Pel Yin}",

year = "2004",

month = jan,

language = "English",

volume = "E87-A",

pages = "275--279",

journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",

issn = "0916-8508",

publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",

number = "1",

}

TY - JOUR

T1 - VLSI Architecture for 2-D 3-Level Lifting-Based Discrete Wavelet Transform

AU - Chen, Pel Yin

PY - 2004/1

Y1 - 2004/1

N2 - Discrete wavelet transform has been successfully used in many image processing applications. In this paper, we present an efficient VLSI architecture for 2-D 3-level lifting-based discrete wavelet transform using the (5, 3) filter. All three-level coefficients are computed interlacingly and periodically to achieve higher hardware utilization and better throughput. In comparison with other VLSI architectures, our architecture requires less size of storage and faster computation speed.

AB - Discrete wavelet transform has been successfully used in many image processing applications. In this paper, we present an efficient VLSI architecture for 2-D 3-level lifting-based discrete wavelet transform using the (5, 3) filter. All three-level coefficients are computed interlacingly and periodically to achieve higher hardware utilization and better throughput. In comparison with other VLSI architectures, our architecture requires less size of storage and faster computation speed.

UR - http://www.scopus.com/inward/record.url?scp=0842288714&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0842288714&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0842288714

SN - 0916-8508

VL - E87-A

SP - 275

EP - 279

JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

IS - 1

ER -

VLSI Architecture for 2-D 3-Level Lifting-Based Discrete Wavelet Transform

摘要

All Science Journal Classification (ASJC) codes

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