VLSI architecture for modified frequency sensitive self-organizing neural network for image data compression

Lih-Yih Chiou, Jimmy Limqueco, M. A. Bayoumi

研究成果: Paper

摘要

We present an adaptive neural network processor for image compression based on a modified frequency-sensitive self-organization algorithm. In this algorithm updating the codevector has a complexity of O(1) and O(N) for best case and worst case situations respectively. Experiments have shown that the worst case situation occurs only at the beginning stage of the learning process. The performance improves as the learning continues. Also the utilization of learning neurons has been considerably increased compared to other algorithm. This algorithm not only achieves a near-optimal result which is comparable with Linde-Buzo-Gray (LBG), but also retains the simplicity for hardware implementation. A mixed-signal architecture is proposed for this algorithm. It consists of analog circuitry which is responsible for neutral network computation and digital circuitry for frequency updating and losers selection.

原文English
頁面418-424
頁數7
出版狀態Published - 1994 十二月 1
事件Proceedings of the 1994 IEEE International Workshop VLSI Signal Processing - La Jolla, CA, USA
持續時間: 1994 十月 261994 十月 28

Other

OtherProceedings of the 1994 IEEE International Workshop VLSI Signal Processing
城市La Jolla, CA, USA
期間94-10-2694-10-28

    指紋

All Science Journal Classification (ASJC) codes

  • Signal Processing

引用此

Chiou, L-Y., Limqueco, J., & Bayoumi, M. A. (1994). VLSI architecture for modified frequency sensitive self-organizing neural network for image data compression. 418-424. 論文發表於 Proceedings of the 1994 IEEE International Workshop VLSI Signal Processing, La Jolla, CA, USA, .