VLSI architecture of extended in-place path metric update for Viterbi decoders

Efficient memory management is always the key technique for successfully designing the Viterbi decoders. In this paper, a novel and efficient in-place scheduling approach of path metric update and its hardware implementation are developed to increase the equivalent memory bandwidth with limited hardware overhead. The resulting architecture has the following characteristics: (I) The whole memory call be systematically partitioned into several sets of banks and each set can be treated as a local memory of a specific add compare select (ACS) unit. (II) The interconnects between the memory banks and ACS units as well as those between adjacent ACS units an regular and simple such that it is very suitable for VLSI array implementation. Our approach can not only provide a methodology for designing high-performance Viterbi decoders, but also give the trade-off between hardware requirement and computation time for updating path metrics, especially for the convolutional code with larger memory order.