## 摘要

This paper presents a high-radix modular multiplication algorithm and its corresponding VLSI architecture for RSA cryptosystem. To reduce the total number of required operations, we partition the multiplier operand into several equal-sized segments and treat each segment as a basic unit for accumulation and modulo operations. Then, the multiplication and residue calculation of each segment are performed in a pipelined fashion to increase the throughput rate. This paper also shows how to simplify the quotient estimation based on multiple-bit overlapping scanning and to reduce the logic depth in high-radix implementation. Results show that only a small lookup table is needed for quotient estimation in our development and the total operating time is smaller than that of the corresponding radix-2 implementation.

原文 | English |
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主出版物標題 | Proceedings - IEEE International Symposium on Circuits and Systems |

發行者 | IEEE |

卷 | 1 |

ISBN（列印） | 0780354729 |

出版狀態 | Published - 1999 |

事件 | Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99 - Orlando, FL, USA 持續時間: 1999 5月 30 → 1999 6月 2 |

### Other

Other | Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99 |
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城市 | Orlando, FL, USA |

期間 | 99-05-30 → 99-06-02 |

## All Science Journal Classification (ASJC) codes

- 電氣與電子工程