VLSI architecture of fast high-radix modular multiplication for RSA cryptosystem

Che Han Wu, Ming-Der Shieh, Chien Hsing Wu, Ming Hwa Sheu, Jia Lin Sheu

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

This paper presents a high-radix modular multiplication algorithm and its corresponding VLSI architecture for RSA cryptosystem. To reduce the total number of required operations, we partition the multiplier operand into several equal-sized segments and treat each segment as a basic unit for accumulation and modulo operations. Then, the multiplication and residue calculation of each segment are performed in a pipelined fashion to increase the throughput rate. This paper also shows how to simplify the quotient estimation based on multiple-bit overlapping scanning and to reduce the logic depth in high-radix implementation. Results show that only a small lookup table is needed for quotient estimation in our development and the total operating time is smaller than that of the corresponding radix-2 implementation.

原文English
主出版物標題Proceedings - IEEE International Symposium on Circuits and Systems
發行者IEEE
1
ISBN(列印)0780354729
出版狀態Published - 1999
事件Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99 - Orlando, FL, USA
持續時間: 1999 5月 301999 6月 2

Other

OtherProceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99
城市Orlando, FL, USA
期間99-05-3099-06-02

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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