TY - JOUR
T1 - VLSI Architecture of S-Box with High Area Efficiency Based on Composite Field Arithmetic
AU - Teng, You Tun
AU - Chin, Wen Long
AU - Chang, Deng Kai
AU - Chen, Pei Yin
AU - Chen, Pin Wei
N1 - Publisher Copyright:
© 2013 IEEE.
PY - 2022
Y1 - 2022
N2 - This work aims at optimizing the hardware implementation of the SubBytes and inverse SubBytes operations in the advanced encryption standard (AES). To this, the composite field arithmetic (CFA) is employed to optimize all building blocks in S-box (and inverse S-box) of SubBytes (and inverse SubBytes) transformation. A joint design of S-box and inverse S-box is also proposed to further enhance the area efficiency. Specifically, the area of multiplier in the Galois composite field, GF ((22)2, is reduced. The squaring and multiplication with constant λ in GF ((22)2 are combined and optimized as well. Moreover, the multiplicative inversion in GF ((22)2 is manually optimized. Furthermore, the S-box and inverse S-box are combined and optimized using the pre_processing and post_processing modules. To increase the throughput, a balanced and pipelined architecture is derived. Using the proposed architecture, a throughput of 5.79 Gbps for the S-box can be achieved on Virtex-6 XC6VLX240T and 10% better than the conventional work. According to the ASIC implementation result, the proposed design can still achieve the highest area efficiency and approximately 30% better than conventional works using TSMC 90nm process.
AB - This work aims at optimizing the hardware implementation of the SubBytes and inverse SubBytes operations in the advanced encryption standard (AES). To this, the composite field arithmetic (CFA) is employed to optimize all building blocks in S-box (and inverse S-box) of SubBytes (and inverse SubBytes) transformation. A joint design of S-box and inverse S-box is also proposed to further enhance the area efficiency. Specifically, the area of multiplier in the Galois composite field, GF ((22)2, is reduced. The squaring and multiplication with constant λ in GF ((22)2 are combined and optimized as well. Moreover, the multiplicative inversion in GF ((22)2 is manually optimized. Furthermore, the S-box and inverse S-box are combined and optimized using the pre_processing and post_processing modules. To increase the throughput, a balanced and pipelined architecture is derived. Using the proposed architecture, a throughput of 5.79 Gbps for the S-box can be achieved on Virtex-6 XC6VLX240T and 10% better than the conventional work. According to the ASIC implementation result, the proposed design can still achieve the highest area efficiency and approximately 30% better than conventional works using TSMC 90nm process.
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U2 - 10.1109/ACCESS.2021.3139040
DO - 10.1109/ACCESS.2021.3139040
M3 - Article
AN - SCOPUS:85122279783
SN - 2169-3536
VL - 10
SP - 2721
EP - 2728
JO - IEEE Access
JF - IEEE Access
ER -