VLSI Architecture of S-Box with High Area Efficiency Based on Composite Field Arithmetic

You Tun Teng, Wen Long Chin, Deng Kai Chang, Pei Yin Chen, Pin Wei Chen

研究成果: Article同行評審

2 引文 斯高帕斯(Scopus)


This work aims at optimizing the hardware implementation of the SubBytes and inverse SubBytes operations in the advanced encryption standard (AES). To this, the composite field arithmetic (CFA) is employed to optimize all building blocks in S-box (and inverse S-box) of SubBytes (and inverse SubBytes) transformation. A joint design of S-box and inverse S-box is also proposed to further enhance the area efficiency. Specifically, the area of multiplier in the Galois composite field, GF ((22)2, is reduced. The squaring and multiplication with constant λ in GF ((22)2 are combined and optimized as well. Moreover, the multiplicative inversion in GF ((22)2 is manually optimized. Furthermore, the S-box and inverse S-box are combined and optimized using the pre_processing and post_processing modules. To increase the throughput, a balanced and pipelined architecture is derived. Using the proposed architecture, a throughput of 5.79 Gbps for the S-box can be achieved on Virtex-6 XC6VLX240T and 10% better than the conventional work. According to the ASIC implementation result, the proposed design can still achieve the highest area efficiency and approximately 30% better than conventional works using TSMC 90nm process.

頁(從 - 到)2721-2728
期刊IEEE Access
出版狀態Published - 2022

All Science Journal Classification (ASJC) codes

  • 電腦科學(全部)
  • 材料科學(全部)
  • 工程 (全部)


深入研究「VLSI Architecture of S-Box with High Area Efficiency Based on Composite Field Arithmetic」主題。共同形成了獨特的指紋。