VLSI design of area-efficient memory access architectures for quasi-cyclic LDPC codes

Ming-Der Shieh, Shih Hao Fang, Shing Chung Tang, Der Wei Yang

研究成果: Conference contribution

摘要

This paper proposes an area-efficient memory access architecture that merges small memory blocks into memory groups to relax the effect of peripherals in small memory blocks. An efficient algorithm is also presented to handle the additional delay elements. The proposed LDPC decoder has the lowest area complexity among related studies.

原文English
主出版物標題Proceedings - IEEE International SOC Conference, SOCC 2011
頁面242-246
頁數5
DOIs
出版狀態Published - 2011 12月 28
事件24th IEEE International System on Chip Conference, SOCC 2011 - Taipei, Taiwan
持續時間: 2011 9月 262011 9月 28

出版系列

名字International System on Chip Conference
ISSN(列印)2164-1676
ISSN(電子)2164-1706

Other

Other24th IEEE International System on Chip Conference, SOCC 2011
國家/地區Taiwan
城市Taipei
期間11-09-2611-09-28

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 控制與系統工程
  • 電氣與電子工程

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