VLSI design of RSA cryptosystem based on the Chinese remainder theorem

Chung Hsien Wu, Jin Hua Hong, Cheng Wen Wu

研究成果: Article同行評審

7 引文 斯高帕斯(Scopus)

摘要

This paper presents the design and implementation of a systolic RSA cryptosystem based on a modified Montgomery's algorithm and the Chinese Remainder Theorem (CRT) technique. The CRT technique improves the throughput rate up to 4 times in the best case. The processing unit of the systolic array has 100% utilization because of the proposed block interleaving technique for multiplication and square operations in the modular exponentiation algorithm. For 512-bit inputs, the number of clock cycles needed for a modular exponentiation is about 0.13 to 0.24 million. The critical path delay is 6.13ns using a 0.6μm CMOS technology. With a 150 MHz clock, we can achieve an encryption/decryption rate of about 328 to 578 Kb/s.

原文English
頁(從 - 到)967-979
頁數13
期刊Journal of Information Science and Engineering
17
發行號6
出版狀態Published - 2001 十一月 1

All Science Journal Classification (ASJC) codes

  • 軟體
  • 人機介面
  • 硬體和架構
  • 圖書館與資訊科學
  • 計算機理論與數學

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