Wafer size MOS2 with few monolayer synthesized by H2S sulfurization

Yen Teng Ho; Yung Ching Chu; Lin Lung Wei; Tien Tung Luong; Chih Chien Lin; Chun Hung Cheng; Hung Ru Hsu; Yung Yi Tu; Edward Yi Chang

doi:10.1109/CSTIC.2017.7919883

Wafer size MOS₂ with few monolayer synthesized by H₂S sulfurization

Yen Teng Ho, Yung Ching Chu, Lin Lung Wei, Tien Tung Luong, Chih Chien Lin, Chun Hung Cheng, Hung Ru Hsu, Yung Yi Tu, Edward Yi Chang

研究教育組

研究成果: Conference contribution

摘要

Wafer sized, high quality continuous films would be a key demand for MoS₂ implemented in circuit application. In this study, the growth of few monolayer Mo_S2 on 4 inches SiO₂/Si substrate were demonstrated. The MoS₂ thin films were synthesized by sulfurized in a furnace from the ultra-thin MoO₃ starting materials by using H₂S. The obtained MoS₂ thin film examined by Raman analysis and Photoluminescence (PL), shows the semiconductor nature with direct transition peaks of 1.86 eV and 1.99 eV. The 4∼5 monolayer of MoS₂ with thickness around 2.6 nm is confirmed by cross-sectional view of transmission electron microscopy (TEM). Additionally, the DC characteristics of MoS₂ MOSFETs exhibit at least 2 order in on/off current ratio, demonstrating the feasibility for circuit application.

原文	English
主出版物標題	China Semiconductor Technology International Conference 2017, CSTIC 2017
編輯	Steve Liang, Ying Shi, Ru Huang, Qinghuang Lin, David Huang, Hanming Wu, Yuchun Wang, Cor Claeys, Kafai Lai, Ying Zhang, Peilin Song, Viyu Shi, Zhen Guo
發行者	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子）	9781509066940
DOIs	https://doi.org/10.1109/CSTIC.2017.7919883
出版狀態	Published - 2017 5月 4
事件	2017 China Semiconductor Technology International Conference, CSTIC 2017 - Shanghai, China 持續時間: 2017 3月 12 → 2017 3月 13

出版系列

名字	China Semiconductor Technology International Conference 2017, CSTIC 2017

Conference

Conference	2017 China Semiconductor Technology International Conference, CSTIC 2017
國家/地區	China
城市	Shanghai
期間	17-03-12 → 17-03-13

All Science Journal Classification (ASJC) codes

工業與製造工程
電子、光磁材料

存取文件

10.1109/CSTIC.2017.7919883

其它文件與鏈接

引用此

Ho, Y. T., Chu, Y. C., Wei, L. L., Luong, T. T., Lin, C. C., Cheng, C. H., Hsu, H. R., Tu, Y. Y., & Chang, E. Y. (2017). Wafer size MOS₂ with few monolayer synthesized by H₂S sulfurization. 於 S. Liang, Y. Shi, R. Huang, Q. Lin, D. Huang, H. Wu, Y. Wang, C. Claeys, K. Lai, Y. Zhang, P. Song, V. Shi, & Z. Guo (編輯), China Semiconductor Technology International Conference 2017, CSTIC 2017 文章 7919883 (China Semiconductor Technology International Conference 2017, CSTIC 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CSTIC.2017.7919883

Ho, Yen Teng ; Chu, Yung Ching ; Wei, Lin Lung 等. / Wafer size MOS₂ with few monolayer synthesized by H₂S sulfurization. China Semiconductor Technology International Conference 2017, CSTIC 2017. 編輯 / Steve Liang ; Ying Shi ; Ru Huang ; Qinghuang Lin ; David Huang ; Hanming Wu ; Yuchun Wang ; Cor Claeys ; Kafai Lai ; Ying Zhang ; Peilin Song ; Viyu Shi ; Zhen Guo. Institute of Electrical and Electronics Engineers Inc., 2017. (China Semiconductor Technology International Conference 2017, CSTIC 2017).

@inproceedings{50d1ea05e51c4593bf757a99bac69cc5,

title = "Wafer size MOS2 with few monolayer synthesized by H2S sulfurization",

abstract = "Wafer sized, high quality continuous films would be a key demand for MoS2 implemented in circuit application. In this study, the growth of few monolayer MoS2 on 4 inches SiO2/Si substrate were demonstrated. The MoS2 thin films were synthesized by sulfurized in a furnace from the ultra-thin MoO3 starting materials by using H2S. The obtained MoS2 thin film examined by Raman analysis and Photoluminescence (PL), shows the semiconductor nature with direct transition peaks of 1.86 eV and 1.99 eV. The 4∼5 monolayer of MoS2 with thickness around 2.6 nm is confirmed by cross-sectional view of transmission electron microscopy (TEM). Additionally, the DC characteristics of MoS2 MOSFETs exhibit at least 2 order in on/off current ratio, demonstrating the feasibility for circuit application.",

author = "Ho, {Yen Teng} and Chu, {Yung Ching} and Wei, {Lin Lung} and Luong, {Tien Tung} and Lin, {Chih Chien} and Cheng, {Chun Hung} and Hsu, {Hung Ru} and Tu, {Yung Yi} and Chang, {Edward Yi}",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 2017 China Semiconductor Technology International Conference, CSTIC 2017 ; Conference date: 12-03-2017 Through 13-03-2017",

year = "2017",

month = may,

day = "4",

doi = "10.1109/CSTIC.2017.7919883",

language = "English",

series = "China Semiconductor Technology International Conference 2017, CSTIC 2017",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

editor = "Steve Liang and Ying Shi and Ru Huang and Qinghuang Lin and David Huang and Hanming Wu and Yuchun Wang and Cor Claeys and Kafai Lai and Ying Zhang and Peilin Song and Viyu Shi and Zhen Guo",

booktitle = "China Semiconductor Technology International Conference 2017, CSTIC 2017",

address = "United States",

}

Ho, YT, Chu, YC, Wei, LL, Luong, TT, Lin, CC, Cheng, CH, Hsu, HR, Tu, YY & Chang, EY 2017, Wafer size MOS₂ with few monolayer synthesized by H₂S sulfurization. 於 S Liang, Y Shi, R Huang, Q Lin, D Huang, H Wu, Y Wang, C Claeys, K Lai, Y Zhang, P Song, V Shi & Z Guo (編輯), China Semiconductor Technology International Conference 2017, CSTIC 2017., 7919883, China Semiconductor Technology International Conference 2017, CSTIC 2017, Institute of Electrical and Electronics Engineers Inc., 2017 China Semiconductor Technology International Conference, CSTIC 2017, Shanghai, China, 17-03-12. https://doi.org/10.1109/CSTIC.2017.7919883

Wafer size MOS₂ with few monolayer synthesized by H₂S sulfurization. / Ho, Yen Teng; Chu, Yung Ching; Wei, Lin Lung 等.
China Semiconductor Technology International Conference 2017, CSTIC 2017. 編輯 / Steve Liang; Ying Shi; Ru Huang; Qinghuang Lin; David Huang; Hanming Wu; Yuchun Wang; Cor Claeys; Kafai Lai; Ying Zhang; Peilin Song; Viyu Shi; Zhen Guo. Institute of Electrical and Electronics Engineers Inc., 2017. 7919883 (China Semiconductor Technology International Conference 2017, CSTIC 2017).

研究成果: Conference contribution

TY - GEN

T1 - Wafer size MOS2 with few monolayer synthesized by H2S sulfurization

AU - Ho, Yen Teng

AU - Chu, Yung Ching

AU - Wei, Lin Lung

AU - Luong, Tien Tung

AU - Lin, Chih Chien

AU - Cheng, Chun Hung

AU - Hsu, Hung Ru

AU - Tu, Yung Yi

AU - Chang, Edward Yi

PY - 2017/5/4

Y1 - 2017/5/4

N2 - Wafer sized, high quality continuous films would be a key demand for MoS2 implemented in circuit application. In this study, the growth of few monolayer MoS2 on 4 inches SiO2/Si substrate were demonstrated. The MoS2 thin films were synthesized by sulfurized in a furnace from the ultra-thin MoO3 starting materials by using H2S. The obtained MoS2 thin film examined by Raman analysis and Photoluminescence (PL), shows the semiconductor nature with direct transition peaks of 1.86 eV and 1.99 eV. The 4∼5 monolayer of MoS2 with thickness around 2.6 nm is confirmed by cross-sectional view of transmission electron microscopy (TEM). Additionally, the DC characteristics of MoS2 MOSFETs exhibit at least 2 order in on/off current ratio, demonstrating the feasibility for circuit application.

AB - Wafer sized, high quality continuous films would be a key demand for MoS2 implemented in circuit application. In this study, the growth of few monolayer MoS2 on 4 inches SiO2/Si substrate were demonstrated. The MoS2 thin films were synthesized by sulfurized in a furnace from the ultra-thin MoO3 starting materials by using H2S. The obtained MoS2 thin film examined by Raman analysis and Photoluminescence (PL), shows the semiconductor nature with direct transition peaks of 1.86 eV and 1.99 eV. The 4∼5 monolayer of MoS2 with thickness around 2.6 nm is confirmed by cross-sectional view of transmission electron microscopy (TEM). Additionally, the DC characteristics of MoS2 MOSFETs exhibit at least 2 order in on/off current ratio, demonstrating the feasibility for circuit application.

UR - http://www.scopus.com/inward/record.url?scp=85020054122&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85020054122&partnerID=8YFLogxK

U2 - 10.1109/CSTIC.2017.7919883

DO - 10.1109/CSTIC.2017.7919883

M3 - Conference contribution

AN - SCOPUS:85020054122

T3 - China Semiconductor Technology International Conference 2017, CSTIC 2017

BT - China Semiconductor Technology International Conference 2017, CSTIC 2017

A2 - Liang, Steve

A2 - Shi, Ying

A2 - Huang, Ru

A2 - Lin, Qinghuang

A2 - Huang, David

A2 - Wu, Hanming

A2 - Wang, Yuchun

A2 - Claeys, Cor

A2 - Lai, Kafai

A2 - Zhang, Ying

A2 - Song, Peilin

A2 - Shi, Viyu

A2 - Guo, Zhen

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2017 China Semiconductor Technology International Conference, CSTIC 2017

Y2 - 12 March 2017 through 13 March 2017

ER -

Ho YT, Chu YC, Wei LL, Luong TT, Lin CC, Cheng CH 等. Wafer size MOS₂ with few monolayer synthesized by H₂S sulfurization. 於 Liang S, Shi Y, Huang R, Lin Q, Huang D, Wu H, Wang Y, Claeys C, Lai K, Zhang Y, Song P, Shi V, Guo Z, 編輯, China Semiconductor Technology International Conference 2017, CSTIC 2017. Institute of Electrical and Electronics Engineers Inc. 2017. 7919883. (China Semiconductor Technology International Conference 2017, CSTIC 2017). doi: 10.1109/CSTIC.2017.7919883