3D-IC Built-In Diagnosis Architecture for TSVs with Different Placement and Impact Ranges of Crosstalk Faults

  • 許 文軒

學生論文: Master's Thesis

摘要

Through Silicon Vias (TSVs) play an important role in 3D chip integration By providing vertical interconnection routing area can be decreased and bandwidth can be increased Effective and efficient testing for correct operation of TSVs is essential for 3D IC design This work addresses the post-bond test and diagnosis of crosstalk faults among TSVs considering different impact ranges and proposes a TSV grouping method for rectangular and hexagonal TSV placements such that as many TSVs as possible are tested simultaneously Based on the results of the TSV grouping we implement a high-efficiency low-area-overhead TSV test architecture that reuses the existing boundary scan or IEEE 1500 wrapper cells typically present for pre-bond testing Experimental results show the low test and diagnosis time as well as the low area overhead of the proposed test architecture
獎項日期2016 二月 16
原文English
監督員Kuen-Jong Lee (Supervisor)

引用此文

3D-IC Built-In Diagnosis Architecture for TSVs with Different Placement and Impact Ranges of Crosstalk Faults
文軒, 許. (Author). 2016 二月 16

學生論文: Master's Thesis