A 0 5-to-3 0 Gb/s Dual Edge Sampling Delay-Locked Loop Based Clock and Data Recovery Circuit

論文翻譯標題: 一個基於雙緣取樣式延遲鎖定迴路並操作於0 5 Gb/s至3 Gb/s之時脈與資料回復電路
  • 吳 繼仁

學生論文: Master's Thesis


This thesis presents a 0 5-to-3 0 Gb/s dual edge sampling DLL-CDR for clock-embedded intra-panel interface applications By combining the proposed dual edge sampling and half-UI embedded clock coding the proposed DLL can save 4 times number of the required delay cells compared to the conventional DLL which not only enhancing the power efficiency but also reducing silicon area With a proper data coding method and the enhanced mask circuit the delay tolerance is increased two-fold making this CDR circuit more robust This CDR circuit is designed and fabricated in TSMC 180-nm CMOS process The measured root mean square (rms) jitter ratio of the rising edge and falling edge of the recovered clock at 3 0 Gb/s are 3 6 % UI and 3 5 % UI respectively The core area of the test chip is 0 519*0 137 mm2 and its power efficiency is 1 43 mW/Gb/s
獎項日期2014 8月 20
監督員Soon-Jyh Chang (Supervisor)