A 0 5-to-5 Gbps Continuous Rate Clock and Data Recovery Circuit with Bi-directional Frequency Detection

  • 陳 彥錡

學生論文: Master's Thesis

摘要

This thesis presents a continuous rate clock and data recovery circuit with bi-directional frequency detection In this work rotational frequency detector and sub-harmonic tone detection technique are combined to widen the frequency range accompanied with bi-directional detection characteristic that is desirable in wide range operation Based on the proposed frequency detection methodology a proof-of-concept clock and data recovery circuit is implemented The clock and data recovery circuit is fabricated in a TSMC 0 18-?m CMOS process The core area is 0 137 mm2 The power consumption of this CDR circuit is 121 1 mW for a supply of 1 8V when input data rate is 0 5 Gbps The root-mean-square (RMS) jitter of recovered clock is 15 9 ps and peak-to-peak (p-p) jitter of recovered clock is 107 5 ps Moreover when input data rate is 4 Gbps the RMS jitter of recovered clock is 17 3 ps and p-p jitter of recovered clock is 92 5 ps The power consumption is 132 1 mW
獎項日期2014 三月 7
原文English
監督員Soon-Jyh Chang (Supervisor)

引用此文

A 0 5-to-5 Gbps Continuous Rate Clock and Data Recovery Circuit with Bi-directional Frequency Detection
彥錡, 陳. (Author). 2014 三月 7

學生論文: Master's Thesis