A Dual-Loop Wide-Range Analog Delay Lock Loop with a Frequency Detector

摘要

This thesis proposes a delay lock loop that operates over a wide frequency range and exhibits good jitter performance The adopted frequency detector determines the current for the charge pump which can improve the nonlinear delay gain of the voltage-controlled delay line to maintain the jitter performance and the locking time Besides a dual loop is applied in the system to minimize the dead zone of the phase detector increasing the jitter performance The proposed DLL has been fabricated by UMC 0 18-?m 1P6M CMOS technology and the core area of the chip is 0 14 mm2 Simulation results show that the proposed DLL can achieve the frequency range from 20 MHz to 1 GHz at 1 8 V supply voltage When the operation frequency is 1 GHz the peak-to-peak jitter is 21 ps and the power consumption is 20 9 mW

獎項日期	2017 2月 9
原文	English
監督員	Bin-Da Liu (Supervisor)