A Low Energy Consumption 10-Bit 100kS/s SAR ADC with Time-based Adaptive Window

  • 孔 致遠

學生論文: Master's Thesis

摘要

This thesis presents a 0 35 V 100 kS/s 10-bit successive approximation register (SAR) ADC with adaptive window (AW) in 90 nm CMOS The SAR ADC uses the transient information of the latch comparator to create redundancy ranges Furthermore the proposed technique also uses the transient information to produce AW for each bit which reduces the power consumption of the comparator the DAC and also digital control logic Last but not least the timing control window can also decrease the possibility ADC from encountering meta-stability The measurement result achieves an SNDR of 57 18 dB an ENOB of 9 2 bits a power consumption of 74 nW and a resulting FoM of 1 25 fJ/conv -step
獎項日期2018 八月 31
原文English
監督員Soon-Jyh Chang (Supervisor)

引用此

A Low Energy Consumption 10-Bit 100kS/s SAR ADC with Time-based Adaptive Window
致遠, 孔. (Author). 2018 八月 31

學生論文: Master's Thesis