A Memory-Efficient NoC System for Manycore Platform

論文翻譯標題: 應用於多核心平台之高效率記憶體網路晶片系統
  • 嚴 健瑄

學生論文: Master's Thesis


Interconnection and memory performance plays an important role in the contemporary parallel computing system In this thesis we evaluate a full system ARM-based many-core platform under the OpenCL framework by offloading the kernel programs into the many-core processors The memory access time dominates the total execution time for the many-core processors in the execution of the memory-intensive OpenCL application Despite the fact that the physical bandwidth provided by the interconnection and memory controllers are very sufficient to the average bandwidth requirement of the applications the memory contention overheads dramatically increase with the scaled system resulting to the poor scalability of the many-core platform Therefore we first develop a configurable mesh NoC system with higher interconnection bandwidth than the conventional bus-based on-chip interconnections However we find that the native NoC has only limited improvement compared to the interconnection matrix in the execution of the memory-intensive OpenCL application Then we integrate the DRAM memory access scheduling approach into the native NoC system to advance the overall memory performance up to 20% More importantly benefited by the packet-switch feature of the NoC the performance improvement due to the memory access scheduling approach grows with the scaled system matching the scalability requirement of the many-core system In the execution of the memory-intensive OpenCL applications the proposed the memory-efficient NoC system effectively upgrades the scalability and memory performance for the many-core platform
獎項日期2014 八月 22
監督員Chung-Ho Chen (Supervisor)