A PVT-Variation Tolerant and High Power-Efficient Sub-threshold SRAMs with Read Leakage Sensing

論文翻譯標題: 具有偵測讀取漏電流且有製程、電壓、溫度變異容忍性與高?率效益之次臨界電壓隨機存取記憶體
  • 鄭 昌杰

學生論文: Master's Thesis


Power consumption is one of important issues in power constraint applications such as wireless sensor networks (WSN) For these power constraint applications we need a low power system-on-a-chip (SoC) to extend life time In breakdown of power consumption SRAMs are one of major sources of power consumption in the SoC Scaling supply voltage into near-threshold or sub-threshold region is one of effective techniques to reduce power consumption However severe variations may occur in the near-threshold and the sub-threshold region For a read-decoupled SRAM read failures may happen because the current ratio between a keeper and a pull-down network has large variations In this thesis we propose a local column sensing keeper scheme to detect the variations and adaptively generate a proper keeper current to deal with the read functionality issues Meanwhile power consumption is reduced by minimizing the keeper contention current A test chip is fabricated using TSMC 90nm technology to demonstrate the proposed SRAM According to post-layout simulation results the proposed scheme supports near-threshold and sub-threshold operation and achieves 24% power reduction when compared with state-of-the-art designs in the worst leakage case
獎項日期2014 9月 10
監督員Lih-Yih Chiou (Supervisor)