This thesis presents an on/off keying wake-up receiver (WuRx) for ultra-low applications Due to the double-sampling technique and passive amplification of the RF gain stage the 2 4 GHz WuRx achieves -51 5 dBm sensitivity at 200 kbps while consuming 25 μW from a 1V supply without LNA VCO and external reference frequency The envelope-detection technique is employed to eliminate the power-hungry LO generation in a super-heterodyne receiver In addition the passive amplification of the input matching network is employed to remove the power-thirsty LNA At the baseband the data is synchronized with the bit clock which is generated from the clock and data recovery (CDR) circuit The CDR consists of a clock recovery circuit (CRC) and D flip-flop The CRC includes an injection-locked oscillator (ILO) and a short pulse generator The clock is multiplied by 4 for generation of sampling clocks The sampling clocks are used to sample the RF and IF signals to achieve a double-sampling technique and to remove 1/f noise and offset voltage The WuRx is fully integrated except an external input matching network A prototype is fabricated in 90 nm TSMC technology The chip area is 1 × 0 95 mm2
A Reference-Less Ultra-Low Power Wake-Up Receiver with Double-Sampling Technique for Wireless Sensor Networks
志軒, 林. (Author). 2016 9月 2
學生論文: Master's Thesis