An 8 Gb/s Half-rate Digital-based Clock and Data Recovery Circuit With Compact Control Loop

  • 鄭 宇栢

學生論文: Master's Thesis

摘要

This thesis presents a compact control loop and a digitalized stepwise control method to improve area and power efficiency performance for digital-based CDRs By combining the frequency control loop and integral path with a digital adder some tributary circuits are removed to save total area and power Meanwhile the stepwise control technique proposed in [9] for constant system bandwidth is digitalized to enhance the system robustness The digital-based CDR is designed and fabricated in 90-nm GUTM CMOS process The measured root mean square (rms) jitter ratio of the synchronous clock and recovered data is 3 2% [9 25ps] and 0 048UI [13 66ps] and the peak to peak jitter is 22 5% [64 38ps] and 0 23UI [65 63ps] while the input data pattern is 7Gb/s PRBS7 The core area of the test chip is 0 054 mm2 and its power efficiency is 1 623 mW/Gb/s Keyword: PLL CDR digital-based CDR
獎項日期2015 八月 21
原文English
監督員Soon-Jyh Chang (Supervisor)

引用此

An 8 Gb/s Half-rate Digital-based Clock and Data Recovery Circuit With Compact Control Loop
宇栢, 鄭. (Author). 2015 八月 21

學生論文: Master's Thesis