Design for Clock and Data Recovery Circuits and Quick Estimation for Jitter Tolerance

論文翻譯標題: 時脈與資料回復電路之設計與抖動容忍度的快速估計技術
  • 李 彥龍

學生論文: Doctoral Thesis


Demands for Serializer and De-serializer (SerDes) integrated circuits (ICs) have increased due to the widespread use of Ethernet networks and chip-to-chip interfaces To ensure the input data stream is well recovered in a receiver end the clock and data recovery (CDR) circuits are widely used In a noisy transmission environment which causes poor signal integrity the CDR circuits have to extract the clock information from input data and resample the input data to remove jitter To characterize the capability of tolerating jitter the jitter tolerance performance is a critical indicator but the verification task is time-consuming and costly This dissertation presents three improved circuit techniques for CDRs as follows (1) The proposed dynamic stepwise bang-bang phase detector is a linear-like transfer characteristics but bang-bang operation It not only enlarges the pull-in range but also enhances the jitter performance (2) The proposed unbounded frequency-detection mechanism combines the digital quadricorrelator frequency detector (DQFD) and sub-harmonic tone frequency detector (FD) in wide-range CDRs which achieve automatically frequency detection The unbounded detection mechanism is limited by the data transition density (3) The proposed gated voltage-controlled oscillator (GVCO) with active inductive loading technique instead of the on-chip inductor reduces the power consumption and area Moreover the two half-rate GVCOs are shared between frequency presetting and data recovery modes to remove one superfluous VCO in designing a cascaded CDR In addition to presenting circuit techniques a quick jitter tolerance estimation methodology is proposed in this dissertation The tracking capability of the CDR is obtained by simply inverting the recovered clock to produce a 0 5 unit interval (UI) phase shift and capture the tracking time Based on the obtained tracking capability a quick jitter tolerance estimation technique is proposed to simplify the time-consuming process as well as avoid the costly test equipment
獎項日期2017 2月 15
監督員Soon-Jyh Chang (Supervisor)