Design Techniques for Enhancing Power Efficiency of Delta-Sigma Modulators and Performance of Switched-Capacitor Circuits

論文翻譯標題: 提昇三角積分調變器?耗效率及切換電容電路效能之設計技術
  • 趙 宜任

學生論文: Doctoral Thesis

摘要

This dissertation investigates low-power technologies for delta-sigma modulators (DSMs) toward the wide-bandwidth development and additionally presents two amplifier’s technologies respectively for improving the memory effect resulting from operational amplifier (opamp) sharing and saving the unnecessary opamp power for the discrete-time switched-capacitor (SC) circuits For the DSM part the techniques both on architectural and circuit level to achieve the low-power purpose are presented The proposed three third-order low-distortion DSM structures are capable of minimizing the number of used opamps and maximizing the utilization of their power; they prolong the critical feedback path timing to be half clock period leading to that other low-speed but high power-efficient analog-to-digital converter (ADC) types can be adopted as a quantizer and not be confined to the flash ADC anymore For dealing with the mismatch of the feedback digital-to-analog converter (DAC) a simplified data weighted averaging (SDWA) algorithm is presented to alleviate not only the nonlinearity but also the hardware implementation compared with the conventional DWA In the first design a double integrator structure is built as the second integrator to enhance the efficiency of opamp sharing applied between the first two integrators A 4-bit cyclic ADC with a loading-free technique is utilized as a quantizer which shares an opamp with the active adder In contrast to the conventional DSM requiring four opamps the proposed structure just employs two opamps including the active adder and quantizer The second design is to simplify the modulator structure of the first one and just uses single opamp to accomplish third-order noise-shaping ability in the whole circuit To realize the adder in front of quantizer without employing the huge-power opamp a capacitive passive adder which is the DAC array of a 4-bit successive-approximation-type quantizer is used The third design merges the active adder into the last integrator and exploits the timing-sharing technique between the second and third integrators during one clock phase Further since the operation phase of the first integrator is different to those of the second and third ones the three integrators are realized in just single opamp by the opamp sharing Therefore the power consumption can be reduced greatly In the amplifier part three techniques are proffered: The first is a splitable amplifier that can be either decomposed into two identical halves or merged for enhancing the utilization of amplifier power and alleviate the residue of the shared circuit stage In a two-phase clock system the amplifier can be split into two identical small amplifiers in one of the two phases simultaneously for use in two circuits and the two small amplifiers can be merged into one amplifier in the other phase for another circuit Compared with conventional opamp sharing a more power-efficient amplifier arrangement is achieved in split mode Furthermore a partial switchable amplifier based on the concept of the splitable amplifier is proposed to avoid the superfluous power consumption during one of operation phases in SC circuits Depending on the required amplifier bandwidth the selection of the proportion of the switchable part to the always on part can be used to optimize power consumption Finally we propose a split-capacitor time-aligned correlated double sampling (CDS) technique that can resolve both the problems of the double capacitance loading and three phases per operation in conventional CDS technique In addition the capacitor set during prediction phase and extra capacitor for storing the finite gain error can be saved
獎項日期2015 九月 3
原文English
監督員Soon-Jyh Chang (Supervisor)

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