Investigation on Reliability of Positive Bias Stress and Anomalous Subthreshold Swing Reducing of Poly-Si Tunnel Field-Effect Transistor

論文翻譯標題: 穿隧式電晶體之正偏壓可靠度與異常次臨界?幅改善之研究
  • 吳 聲敏

學生論文: Master's Thesis

摘要

In this study we fabricated and demonstrated poly-Si TFTs and poly-Si TFET with positive bias reliability research in low temperature For TFT device it demonstrates higher on current up to 3 08x10-4 A due to carrier transport mechanism of electric field drift and larger effective conduction area Id-Vg curve starts to split up with different subthreshold swing after gate voltage stress The SS shift after 1000sec stress from 0 34V/dec to 0 65V/dec and maximum of transconductance variation Δgmmax from 42μS to 71μS for gate stress 15V and 25 V respectively For TFET device poor S S degradation is due to the low source doping concentration and the trap assisted tunneling (TAT) Positive Bias Stress only improve SS and Vth of TFET without gm We implied two possibilities Firstly stress generated traps be recovered and compensated by electrons might be the reason However as studies shows that the recovery and compensation of traps from carrier are only temporary condition Secondly stress create traps with the same energy level to reduce TAT current Since TAT is dominant TFET degradation of subthreshold region density of traps and trap energy are important for SS behavior If stress change traps energy distribution that produces the same traps level TAT current could be reduce by limiting tunneling direction then suppress SS deterioration
獎項日期2017 一月 19
原文English
監督員Kuo-Hsing Kao (Supervisor)

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