Modeling and Simulation of Strained SiGe TFETs with Vertical Tunneling

論文翻譯標題: 應變矽鍺穿隧場效電晶體之模擬
  • 郭 貫中

學生論文: Master's Thesis


As development of technological technique the requirement of electrical production tend to convenient low power consumption high speed velocity There will cause many difficult problems of manufacture process and device characteristic when scale down traditional MOSFET In order to avoid nonideal phenomenon some novel devices are presented continually In this thesis we will discuss structure of Tunnel FET mainly TFET is a promising device in the future due to it possesses two main advantages: (1) the mechanism of transmission of carriers is by tunneling rather than by diffusion; therefore SS cannot be limited at 60mV/decade (2) Comparing MOSFET with TFET TFET possesses very low off current it properly apply to low operate power or LSTP-Low Standby Power Though TFET possesses two excellent merits on current cannot achieve same level of MOSFET yet Therefore we will concentrate on how to improve performance of TFET In this study we utilize two ways to increase on current The one is using SiGe alloy and strained technique which is generated by growing SiGe on Si-sub Another way is using special structure which include vertical tunneling Finally we will consider some different parameters in TFET’s simulation and analysis corresponding characteristic of different parameters
獎項日期2016 七月 5
監督員Kuo-Hsing Kao (Supervisor)