The Low-power VLSI Design for Sorting Unit and Median Filter

論文翻譯標題: 低?耗排序單元與中值濾波器之VLSI設計
  • 林 世祥

學生論文: Doctoral Thesis


This thesis presents hardware design and implementation of sorting algorithm and median filter architecture There are mainly three portion in this thesis including the design of low-power sorting unit design of low-power median filter and modular design of bit-level median filter The dynamic power dissipation of VSLI is analyzed when designing low-power sorting unit The data migration in register or signal transition is minimized in order to reduce the total power consumption The comparing modules move the indexes of samples instead of moving the input data directly Statistical analysis is conducted to predict the reduction of switching activities and simulation results highlight the reliability and accuracy of our prediction Experiment results show that the proposed method has lower power dissipation than previous methods had when the systems work on a same clock rate the power consumption is reduced by 64 9% at most and high-throughput performance can also be achieved For median filter a novel FIFO structure and mathematical model for controlling the clock signals attached to circuit is presented by analyzing the behavior of the filter The design immobilizes the data in registers and reduces not only signal transitions but also switching activities thereby reducing the total dynamic power consumption Furthermore the proposed architecture provides high-speed computation Experimental results show that the proposed method is more energy efficient than existing designs The power consumption is reduced by 25 1% on average Bit-level median filter is constructed by modular architecture hierarchically Different types of submodules could be applied to form a customized architecture in order to meet different constraints and requirements Hardware-oriented optimization is performed to achieve the optimal configurations when the input size and data length were changed Resource consumption is reduced by 23 29% when compared to state-of-the-art design The experimental results show that the proposed cascaded architecture is superior to existing designs in terms of maximal operating speed and resource costs The VLSI architectures of the proposed designs were implemented by using Verilog HDL and synthesized by Synopsys Design Compiler with the TSMC 90-nm cell library Synopsys IC Compiler was adopted for automatic placement and routing(APR) Switching activity interchange format (SAIF) files from the post-layout simulation are used to produce reliable measurements of power dissipation
獎項日期2018 二月 9
監督員Pei-Yin Chen (Supervisor)